To reliably write image data, some conventional active-matrix liquid crystal display devices perform a precharge operation in which predetermined potentials are applied to video signal lines immediately before data writing. The configuration and operation of such a liquid crystal display device will be described below.
FIG. 11 is a block diagram illustrating the overall configuration of a conventional active-matrix liquid crystal display device that performs a precharge operation. This liquid crystal display device includes a display control circuit 200, a source driver (video signal line drive circuit) 300, a gate driver (scanning signal line drive circuit) 400, a display portion 500, and precharge switching elements SW(1) to SW(M).
The display portion 500 includes a plurality (M) of video signal lines SL(1) to SL(M), a plurality (N) of scanning signal lines GL(1) to GL(N), a plurality (N) of auxiliary capacitance lines CsL(1) to CsL(N), and a plurality (M×N) of pixel forming portions provided along the video signal lines SL(1) to SL(M) and the scanning signal lines GL(1) to GL(N).
The display control circuit 200 receives a display data signal DAT and a timing control signal TS, which are both externally transmitted, and outputs digital image signals DV, along with a source start pulse signal SSP, a source clock signal SCK, a latch strobe signal LS, a gate start pulse signal GSP, a gate clock signal GCK, and a precharge control signal PC, which are for use in controlling the timing of displaying an image on the display portion 500.
The source driver 300 receives the digital image signals DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS outputted by the display control circuit 200, and applies drive video signals S(1) to S(M) to the video signal lines SL(1) to SL(M) in order to charge pixel capacitances in the pixel forming portions in the display portion 500. At this time, the source driver 300 sequentially holds the digital image signals DV, which indicate voltages to be applied to the video signal lines SL(1) to SL(M), at times of pulse generation by the source clock signal SCK. Thereafter, the digital image signals DV being held are converted into analog voltages at times of pulse generation by the latch strobe signal LS.
On the basis of the gate start pulse signal GSP and the gate clock signal GCK outputted by the display control circuit 200, the gate driver 400 sequentially applies active scanning signals G(1) to G(N) to the scanning signal lines GL(1) to GL(N).
In this manner, in the display portion 500, the digital image signals DV from the source driver 300 are applied to the video signal lines SL(1) to SL(M) as the drive video signals S(1) to S(M), and the scanning signals G(1) to G(N) from the gate driver 400 are applied to the scanning signal lines GL(1) to GL(N), respectively. As a result, voltages in accordance with the drive video signals S(1) to S(M) are held in the pixel capacitances of the display portion 500, and voltages equivalent to potential differences between pixel electrodes and a common electrode are applied to a liquid crystal layer in accordance with the voltages being held. With these voltages applied, the display portion 500 controls the optical transmittance of the liquid crystal layer, so that the image represented by the digital image signals DV received from an external signal source is displayed.
Here, recent advancement of high-resolution display panels demands drive video signals to be charged in pixel capacitances in a shorter period of time, and in some cases, there might be not enough time to complete the charging. Therefore, to appropriately charge the pixel capacitances in a short period of time, an operation (called a precharge operation) in which video signal lines (and, where necessary, pixel capacitances) are precharged by applying a predetermined potential (e.g., a common electrode potential or such like) might be performed prior to application of drive video signals. This will be described below with reference to FIG. 12.
FIG. 12 is a waveform chart of various signals for the conventional liquid crystal display device that performs a precharge operation. Here, alternating-current drive is required in order to prevent deterioration of the liquid crystal layer over time, and therefore, this liquid crystal display device employs a so-called line inversion drive method in which the voltage that is applied to the liquid crystal of the pixel forming portion is reversed in polarity every row and also every frame, and in this case, a common potential Vcom is set as a mid-point voltage (in the variation range) of the video signal. As a result, the potential of the pixel electrode can be converted to alternating-current potential with respect to the potential of the common electrode.
Furthermore, as shown in FIG. 12, a period tp of nonselection is provided between the fall of a scanning signal G(n) and the rise of the next scanning signal G(n+1), and during this period, the precharge control signal PC is turned on. Consequently, as can be appreciated with reference to FIG. 11, a precharge potential PV (e.g., a mid-point voltage) is applied to each of the video signal lines SL(1) to SL(M).
Note that for simplification of the description, the drive video signals S(1) to S(M) are shown in FIG. 12 as not being changed in potential for the period tp, but in actuality, the source driver 300 stops outputting the drive video signals S(1) to S(M), thereby rendering its contacts with the video signal lines SL(1) to SL(M) into the state of high impedance.
In such a state, by performing the precharge operation, the potentials of the video signal lines SL(1) to SL(M) are raised or lowered to voltages (e.g., a mid-point voltage) in accordance with the polarities of the drive video signals S(1) to S(M) to be applied next. As a result, the following pixel capacitance charging can be completed in a short period of time.
Note that in relevance to the present invention, the following prior art documents are known. First, Japanese Laid-Open Patent Publication No. 2001-147420 describes the configuration of a liquid crystal display device in which, to prevent horizontal shadow, a detection bus line which crosses all data lines is provided to detect the sum of outputs from the data lines and adjust a common potential. Second, Japanese Laid-Open Patent Publication No. 11-30975 describes the configuration of a liquid crystal display device in which, to shorten the period of charging/discharging source lines, all of the source lines are short-circuited to a common potential at the beginning of the writing to liquid crystal capacitance. Third, Japanese Laid-Open Patent Publication No. 11-202835 describes the configuration of a liquid crystal display device provided with a circuit for applying an auxiliary voltage prior to application of an inverted output voltage during dot inversion drive. Fourth, Japanese Laid-Open Patent Publication No. 11-271801 describes the configuration of a liquid crystal display device in which all video signal lines are connected to capacitive elements via switches, so that charge provided to the video signal lines is partially stored, and the switches are opened and closed to supply charge to the video signal lines before the next charging. Fifth, Japanese Laid-Open Patent Publication No. 2004-125887 describes the configuration of a liquid crystal display device having a noise suppression wire to which a fixed potential is provided, and also having a capacitor provided between the wire and each data signal line. Sixth, Japanese Laid-Open Patent Publication No. 2006-39337 describes the configuration of a liquid crystal display device in which capacitors to be connected to data lines are interchanged with each other during dot inversion drive in accordance with the polarity of an image signal. Seventh, Japanese Laid-Open Patent Publication No. 2006-126471 describes the configuration of a liquid crystal display device in which a gradation voltage is generated in a predetermined period, and no gradation voltage is generated in other periods. Eighth, Japanese Laid-Open Patent Publication No. 2007-256909 describes the configuration of a liquid crystal display device in which capacitive elements of different capacitance values are provided to data lines in order to reduce uneven luminances. Ninth, Japanese Laid-Open Patent Publication No. 2008-8942 describes the configuration of a liquid crystal display device in which a coupling capacitance having the same laminated structure as a pixel capacitance is provided to each data line in order to reduce uneven luminances as above and also achieve compact size.